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Sunghoon Kim

Engineer at Samsung Electronics

Education

M.Sc in Electrical Engineering

Pohang University of Science and Technology, Pohang, Republic of Korea
Sep. 2018 - Aug. 2020

B.Sc Graduated with Highest Honors in Advanced Material Science(1st), Electrical Engineering (2nd)

Ulsan National Institute of Science and Technology, Ulsan, Republic of Korea
Mar. 2012 - Feb. 2018

Languages

  • Korean (Native)
  • English (Advanced High (OPIC))

Interests

  • Machine Learning / Tabular Dataset and Graph Neural Network
  • VLSI CAD / Design Automation
  • XAI (eXplainable Artificial Intelligence)

About Theme

Career Profile

Sunghoon Kim is a engineer at Samsung Electornics (Foundry). He received a Master of Science degree in the Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Korea in August 2020. Advisor was Prof. Seokhyeong Kang in CAD & SoC Design Lab.
His research interests in Samsung Foundry included AI-based Yield Ramp-up and Electronic Design Automation methodology development. His research interests in POSTECH included energy-efficient deep learning computing at the intersection between machine learning and low power VLSI design. Before joining POSTECH, he received a Bachelor of Science degree with the highest honors in the Material Science Engineering at Ulsan National Institute of Science and Technology (UNIST), Korea in February 2018.

– Last update Jun. 2024 –

Experiences

Engineer

Sep. 2020 - (Ongoing)
Samsung Electornics (Foundry)

Graduate Student

Jun. 2018 - Aug. 2020
CAD & SoC Design Lab in POSTECH, Prof. Seokhyeong Kang
  • Thesis: MDARTS: Multi-objective Differentiable Neural Architecture Search
  • GPA: 4.15/4.3, 2020

Undergraduate Student Researcher

Mar. 2017 - Dec. 2017
Nano Spin Transport Lab in UNIST, Prof. Jung-Woo Yoo

Undergraduate Student Researcher

Jul. 2017
UNIST-Harvard School of Engineering and Applied Science Summer Cross-Cultural Engineering Program, Prof. Fawwaz Habbal (Harvard)

link

Undergraduate Student Researcher

Jul. 2016 - Aug. 2016
Nanomaterials Science and Engineering Lab in UNIST, Prof. Jae Sung Son

Projects

Reducing Circuit Design Backend Flow TAT by Developing ML-based Design Rule Violation Predictor

Samsung Foundry, Jul. 2023 - May. 2024 (11 months)

Circuit PPA push with dso.ai

Samsung Foundry, Aug. 2023 - Oct. 2023 (3 months)

AI-based Yield Prediction and Cause Analysis Methodology Development

Samsung Foundry & Samsung Advanced Institute of Technology et al., Dec. 2020 - Sep. 2023 (2 years and 7 months)

Autonomous Accuracy Scaling for Ultra-low-power Intelligent Mobile Systems

Samsung Science & Technology Foundation, POSTECH, et al., Aug. 2018 - Jun. 2020 (1 year and 9 months)

Deep Learning and Development of Voice Interactive Smart Home Control System based on Internet of Home Things (IoHT)

POSCO Future IT Convergence Research Institute, POSTECH, et al., Dec. 2018 - Jun. 2020 (1 year and 7 months)

Camera-based Real-time Artificial Intelligence System for Detecting Driving Environment Recognizing Objects on Road Simultaneously

National Ressearch Foundation, KETI, POSTECH, DGIST et al., Sep. 2018 - Feb. 2019 (6 months)

Papers

  1. ML-based PPA Push using DRV Prediction
    2. Jungho Kim, Kyeongsun cho, Sunghoon Kim, Mintae Lee and Wook Kim
    Design Automation Conference (DAC), engineer track , 2024
  2. MDARTS Multi-objective Differentiable Neural Architecture Search
    3. Sunghoon Kim, Hyunjeong Kwon, Eunji Kwon, Youngchang Choi, Tae-Hyun Oh and Seokhyeong Kang
    The Design, Automation, and Test in Europe (DATE) Conference , 2021
  3. GRLC Grid-based Run-length Compression for Energy-efficient CNN Accelerator
    4. Yoonho Park, Yesung Kang, Sunghoon Kim, Eunji Kwon and Seokhyeong Kang
    IEEE International Symposium on Low Power Electronics and Design (ISLPED) , 2020
  4. Spatial Correlation-aware Compression Algorithm for Saving DRAM Access Energy
    5. Yoonho Park, Yesung Kang, Sunghoon Kim, Eunji Kwon and Seokhyeong Kang
    Korean Conference on Semiconductors (KCS) , 2020
  5. Analysis and Solution of CNN Accuracy Reduction over Channel Loop Tiling
    6. Yesung Kang, Yoonho Park, Sunghoon Kim, Eunji Kwon, Taeho Lim, Sangyun Oh, Mingyu Woo, and Seokhyeong Kang
    Design, Automation and Test in Europe Conference(DATE), 2020
  6. Analysis and Solution of CNN Accuracy Reduction over Channel Loop Tiling
    7. Yesung Kang, Yoonho Park, Sunghoon Kim and Seokhyeong Kang
    The Institute of Semiconductor Engineers Conference (ISEC), 2018

Patents

  1. NEURAL NETWORK ACCELERATOR AND OPERATING METHOD THEREOF

    2. Seokhyeong Kang, Yesung Kang, Yoonho Park and Sunghoon Kim

    South Korea 10-2019-0034583, Mar 26, 2019 (application)

  2. NEURAL NETWORK ACCELERATOR AND OPERATING METHOD THEREOF

    3. Seokhyeong Kang, Yesung Kang, Yoonho Park and Sunghoon Kim

    United State UP-2900650-US, Jan 24, 2020 (application) link

Awards

  1. SEC Annaual Awards in S/W Division Silver Prize, 2022 (삼성전자), AI-based Foundry Yield Ramp-up Methodology Development

  2. Best paper award at ISLPED, 2020 link

  3. Excellent paper award in VLSI CAD division at KCS, 2020

  4. Best paper award at ISE Conference, 2018

  5. Graduated with highest honors from UNIST: GPA (4.17/4.3), 2018 link

  6. Kyungdong Scholarship for Harvard-UNIST Summer Exchange Program 2017 link

  7. Republic of Korea National Science and Engineering Scholarship, 2012 - 2018

Teachings

I am a teaching assistant for the following courses:

  1. EECE490F: Introduction to VLSI Design, Spring 2019 at POSTECH

  2. Manage CSDL Tutorial Page: https://github.com/CSDL-postech/CSDL_Tutorial

  3. My Study Page: https://github.com/kim-sunghoon/Study-materials

  4. I served as a Samsung Value Program (SVP) Senior as part of the Leadership Development Course (Feb. 2024 - Mar. 2024), 삼성 신입사원 연수프로그램 (SVP) 선배 수행

Skills

Basics - Linux, Git, Python, C++

Machine Learning - PyTorch, Tensorflow, Scikit-learn, Skopt (Bayesian Optimization)

Data Processing & Visualization - Pandas, Matplotlib, Spotfire

Infra - bash/csh dotfiles, AWS s3 & glue, Kubernates

Cadence - NC Verilog & Simvision

Synopsys - Design Compiler, IC Compiler2, Fusion Compiler, Prime Time, DSO.ai

Xilinx-Vivado, High Level Synthesis, Petalinux